Level 1 - Design of a simple parallel Input/Output

One of the most common I/O subsystems is the parallel input or output which uses a simple

n-bit register for storing the output and another one for storing the input. This is very often

called latched I/O, and uses the following structure:

UFMFQT-15-2

UFMFQT-15-2

from outside

↓

to registers

Digital System Design

Digital System Design

Implement the above shown structure in VHDL

Simulate your design and show correct behaviour

from registers

Your submission must include the following:

↓

Two 8bit registers are used in this case. The clock signal on the right structure is controlled

by the executioner, while the clock signal of the left structure is controlled by the outside

environment. Therefore, even short signal changes can be stored in the Input Structure

(left), since the values are stored in the register.

Your task is to:

to outside

All VHDL sources

• Screenshots of the simulation showing correct behaviour

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