2) Next generate a plot for Ip vs Vos for the diode connected NFET over 0-3 V of VDS

bias. Include on your plot the effect of a bulk voltage of -0.5, 0, 0.5 and 1V. The easiest

way to get all 3 curves on the same plot is to use 3 instances of the device in your

simulation schematic, each with different bulk bias voltages. Using NET aliases can be

useful here. Repeat for our PFET but now with bulk bias voltages of 3.5, 3, 2.5 and 2V.

Here you should clearly see the body effect on the transistor characteristic.

Replot these for the square root of ID vs VGs and estimate the effective threshold for each

bulk voltage.

For the NFET

a) Schematic used for the simulation

b) Plot showing the simulation results for ID vs VGs for the different bulk voltages.

c) Plot of the square root of ID vs VGS for the different bulk voltages.

d) A table showing the threshold voltages vs the bulk bias

Then include the same for the PFET.

(need the screenshots for these)

General observations and suggestions: be sure you have a proper ground or the simulator

will not work, it needs to be set as node zero. Setting the bias will be a challenge for

many of you. Think about the meaning of the sign of the current. To make the PFET plots

look "normal" you can change the signs of the voltages and currents plotted as

appropriate. Use enough points in your simulation to make the curves look smooth.

Note:

clearly label the axes, label the traces with the Vgs or

bulk bias voltages used, also make the traces thicker than the default and adjust colors for

readability.

Be careful in your choice of NFET3 or NFET4, only use the 3

terminal version if you are sure that the source voltage will always be at ground for the

NFET. The NFET3 and PFET3 versions have their source and bulk terminals tied

together internally. For our process this cannot be done for the NFET but it can for the

PFET.