2: Construct timing diagram [5 points]

Graph the signals that result for the circuit you drew for Step 1 of the prelab. Assume that the propagation

delay is much shorter than the step size of 1 second per division. In other words, when an input causes an

output transition, you will see it at the same time as the signal that caused the transition. You should also

assume that the initial state of the Q output of the flip-flop is 0.